Why system verilog code? If it's going to be implemented in an FPGA or ASIC, requiring it to be in SV is kind of silly as there really isn't anything specifically special about SV that would improve a Verilog only version, or is the plan to use assertions in your code?
If that's the only reason then just use Google like suggested by erikl and get a Verilog version (change the extension from .v to .sv) and add the assertions.
This might be a typical university exercise.
I remember in our 1st year our professor had given us the assignment to develop a VHDL model of a sigma-delta converter. It was required just to work in simulation, no synthesis. I don't remember anything further after so many years. ;-)