Meenz
Newbie level 5
Hi..
I am tryin to develop a TB for I2C which has a wishbone I/f. I have classified the DUT signals into interfaces.
Now am trying to develop the driver. In I2C there is a continous hanshake and the data has to be input in a particular sequence ( eg send slave address, data etc in sequence). In such a scenario how do i drive input to my DUT? should i say hold my addr, data, we etc in a struct and everytime wait for ack from DUT to proceed next. If thats the case then its almost like a directed test.
For this scenario could anyone suggest how i use System verilog features to build my testbench.
Any help will be deeply appreciated.
Regards
Meenz
I am tryin to develop a TB for I2C which has a wishbone I/f. I have classified the DUT signals into interfaces.
Now am trying to develop the driver. In I2C there is a continous hanshake and the data has to be input in a particular sequence ( eg send slave address, data etc in sequence). In such a scenario how do i drive input to my DUT? should i say hold my addr, data, we etc in a struct and everytime wait for ack from DUT to proceed next. If thats the case then its almost like a directed test.
For this scenario could anyone suggest how i use System verilog features to build my testbench.
Any help will be deeply appreciated.
Regards
Meenz