vishhh11
Newbie level 4
Sir,
In my design , I have to check whether clock period is 2.5ns everytime (at every posedge). How should I write the system verilog assertion to check the clockperiod??? Please help !!
In my design , I have to check whether clock period is 2.5ns everytime (at every posedge). How should I write the system verilog assertion to check the clockperiod??? Please help !!