what's the difference between system generator and simulink HDL coder...?
why should i use one and not the other?
do i see HDL code as an output of both or just .bit files ready for download on FPGA?
system generator is a xilinx product , which is optimized to use xilinx FPGAs , but HDL coder generates verilog and VHDL codes generally without the dependencies on the certain FPGA technology
another thing u can use the output of the HDL coder in ASIC technology
so if my design is going to be implemented on FPGA then i should just use system generator...but i won't get an HDL file, it would be either the netlist or the bit file....but by HDL coder, synthesizable code is generated which can then be altered in any way i want, synthesized and implemented on FPGA or ASIC...