system design using Cyclone II (PLL, buffer etc...)

[allison_www]

Hi,

I am trying to implement a hardware system which uses current to compute distances. The incoming current is obtained from a sensor, and will be sampled and input into my FPGA. The ADC is 14bit, 250MSPS. A lock-in amplifier will be designed within the FPGA to extract the noise from a large amount of noise.
my problem is: the current signal is 154KHz. When I tried to build a PLL module using the ALT_PLL megafunction, the lowest required input frequency is 10MHz...
Now I am thinking of using two PLL modules, one to divide the 10MHz into 154Khz, if that is possible, the other to create its reference signal. Is there a better way?
Also, I guess I need to build a buffer before ADC to store the current. but I dont know what type of buffer / where to get information about that. Could anyone help me? Thanks!

 

[ninju]

Yeah you can feed the output of one pll into another. Else, design a counter which will trigger everytime it overflows. You can dump it into your computer straightaway using signal tap feature.