[Synthethis] ILM - Interface Logic Model

[ivlsi]

Hi All,

As for the Interface Logic Model (ILM) - is this an essential stage in nowadays synthethis techniques?

Could someone provide more details about this stage?

How is Synopsys ICC different from its Design Compiler? What stages were been added?

Thank you!

 

[OhaAmo]

using ILM is to reflect blocks interface timing to higher hierarchies. The top hierarchy needs the blocks interfaces timing for timing fix. So somewhere in the middle of the project (big scale ones) there is a need to all the blocks to preform ILM and to get replays for paths and ports to fix inside the that the top sees.
Usually in this stage only the interface logic remains while the other logic cells are deleted.

 

[ivlsi]

So, the ILM is used when timing fixes are required in the topper hierarchies and lower hierarchies are intended to left untouched. Right?
Why not to use just the 'dont_touch' attribute?
Could ILM be used in the PrimeTime as well?

 

[OhaAmo]

In large project usually there are separate teams who work on the top of the chip and on the IPs.
During the project life cycle there is a constant talk between the 2 teams. In order to give the "top" team the ability to see real timing paths that need to be fixed, the IPs team make ILM of the IPs and reflect the IPs interface to the "top" team. Now the "top" can either decide to fix problematic paths by itself or tighten the timing budget given down to the IP for those paths.

 

[ivlsi]

What pros and cons between creation *.lib files for the lower hierarchies and creation of ILM?

Should the ILM be created as a separate file and then be read/linked/referred from the top hierarchy?

 

[OhaAmo]

I found the following ppt presentation about ILM and .lib files, it contains most of the answers you want.
https://www.ee.bgu.ac.il/~digivlsi/slides/STA_9_1.pdf