[SOLVED] synthesizing the coregen IP

ngdbuild:604 synplicity

Hello;
I have generated my 3-bits registered adder by coregen for synplicity and for spartan (myadder3.vhd the wrapper vhdl file which was produced by coregen); and then instantiated it to my parent file (myadder3_top.vhd). Then I synthesized my prject which only include parent file, by synplifypro. after that when I want to use constraint editor in ISE4.2.0.3 it send the following error message:

Checking expanded design ...
ERROR:NgdBuild:604 - logical block 'myadder' with type 'myadder3' is unexpanded.
Symbol 'myadder3' is not supported in target 'spartan'.

NGDBUILD Design Results Summary:
Number of errors: 1
Number of warnings: 0


One or more errors were found during NGDBUILD. No NGD file will be written.

Writing NGDBUILD log file "myadder3_top.bld"...
EXEWRAP detected a return code of '2' from program 'ngdbuild'

Done: failed with exit code: 0002.



I generate my IP for spartan and based on its datasheet it support spartan so why I received this error?

Added after 25 minutes:

please check the xilinx answer database:


**broken link removed**