p11
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Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 ---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 16:05:19 02/07/2017 -- Design Name: -- Module Name: vhdl_data - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity vhdl_data is port( Clk : in std_logic; -- processing clock we : in std_logic; -- write enable signal data_out : out std_logic_vector(8 downto 0) ); -- output data from memory end vhdl_data; architecture Behavioral of vhdl_data is ------------------------------------ RAM declaration type memory1 is array (0 to 1999) of STD_LOGIC_VECTOR (8 DOWNTO 0); signal dat2 : memory1 :=(others => "000000000"); type memory2 is array (0 to 999) of STD_LOGIC_VECTOR (8 DOWNTO 0); signal dat : memory2 :=(others => "000000000"); -------------------------------------- Signal declaration signal j : integer; signal kout1 : integer:=1; signal k2 : integer; begin process(Clk, we) begin if (rising_edge (clk)) then if we = '1' then -- In this process writing the input data into ram --- dat2 (kout1+conv_integer(dat2(kout1-1))) <= dat (j); -- dat2 (kout1-1) <= dat2 (kout1-1)+1; end if; end if; end process; data_out <= dat2(k2); -- Reading the data from RAM end Behavioral;
This code is taking too long time to synthesize ............. , i mean going on and on ... after 20 mins i stopped it forcefully , so really dont know whether finally it will synthesize or not ... whats the problem with this code ... any modification please .
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