Yes, because you are building HUGE arrays of registers, and not memories, becuase your "memory" signals do not bahave like proper memories:
To make it infer a memory, you need to register the write data and read address. You cannot used the read data to immediatly write back to ram.
I suggest reading some code guidelines on how to infer a ram (or you may be better off just using coregen to create rams for you, and instantiating them yourself)
Here are the Vivado Coding Guidlines- ram is on page 96
https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_1/ug901-vivado-synthesis.pdf
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I also notice you have failed to provide the whole code. - please provide all of the code!