[SOLVED] synthesize of transistor level description in design compiler

[farzaneh_2561]

Hi everybody
Does Design Compiler synthesize a transistor level description and if it doesn't is there any other tool to do so?
thank u.

 

[jrwebsterco]

DC only works at the digital logic cell level (using abstracted models of the cells described in the Liberty format).
And, depending on the cell library you are using (and your licensing arrangement with the library provider), you also might not even have available the SPICE netlists for the cells.
But, if you do the back-end P&R & DRC & LVS in-house, then you might at least have CDL netlists, which are a simplified subset of the full SPICE netlists for the cells (e.g. they only include N/P & W & L params, and are therefore not good for accurate SPICE sims - they are only intended for feeding LVS).

Similarly, DC does not write out a SPICE-format netlist (only structural Verilog, etc.).
However, I'd expect there are translation utilities on the 'net which can convert such a structural Verilog netlist into a SPICE-compatible one, though it will still only be instantiating the cells as subcircuits.
But, this could be combined/included with the aforementioned SPICE netlists for the cells, and you then have a complete transistor-level netlist.
(this is effectively how LVS is run in a synthesized ASIC flow, since it must check down to the transistor layout level)

Note I have not personally searched for free Verilog-to-SPICE translators - I did help develop one in Python once, and subsequently have used ones which are nowadays included with commercial SPICE and LVS tools.
If you have access to such tools, you might already have a translator available (those translator utils don't typically even require a license key - just the installed binary).