Synthesizable division code on VHDL

[sai1711]

Hi All,
I am one of those who uses the FPGA once in a blue moon. As my major part has to deal with Analog field. So am teh worst kinds of newbies you would ever find . :grin:

I have seen a lot of codes on the forum on the aspect of Division VHDL code, I found that they are pretty much useless when we want to implement them onto an FPGA board.
I have the following inferences:
- Is the traditional way of binary division the only way forwards? can any sacred soul confirm this to me? It sucks when u dont have a guide or any colleague who has any idea on this field.


- CORDIC IP core makes the hardware too bulky? Also, I somehow always avoid using cordic ip cores. Prime reason being, there are other shortcut ways of doing the same. e.g. Sinewave generator.


An overview and confirmation from an expert would be a morale booster.

 

[TrickyDicky]

For division - use the Divider IP cores provided by the vendor (altera and xilinx both offer cores for free). They are fully pipelined and customisable so you can get good FMax fom them. using a <= b/c; will only infer the divider with a 1 clock latency, which give a very poor fmax.