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delays are not synthesizeable.
The only option is, to set up a counter which delays the signal by a known 'count' the frequency at which counter works, and the count will determine the delay
Kr,
Avi http://www.vlsiip.com
There is no standard synthesizable delay in VHDL.
You can go for some divide by counters. If you know the clock frequency find a suatable count to so that you get that delay.
a <= b after 50 ns, is not a synthesizable construct.
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