phaneendra.raguru
Newbie level 1
Hi,
i need an array of static values such as
It is compiling in System Verilog but not in Verilog.
Please suggest me the suitable synthesisable verilog code where i can initialize static values
i need an array of static values such as
Code:
reg [7:0] s_box [0:3][0:3] = '{'{8'h0,8'h1,8'h2,8'h3},
'{8'h10,8'h11,8'h12,8'h13},
'{8'h20,8'h21,8'h22,8'h23},
'{8'h30,8'h31,8'h32,8'h33}};
Please suggest me the suitable synthesisable verilog code where i can initialize static values
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