After synthesis, you can check:
- Clock ideal STA. Knowing critical parts about timing in you design functional mode.
- Area ( Without clock cells and optimization cell from PnR ). Inform it to PnR members would be helpful for them.
- SDC quality. ( report by check timing and so on .. )
If you want, you can check power report, but it is not closed to final number because lacking of clock cells and optimization cells.
After synthesis, you can check:
- Clock ideal STA. Knowing critical parts about timing in you design functional mode.
- Area ( Without clock cells and optimization cell from PnR ). Inform it to PnR members would be helpful for them.
- SDC quality. ( report by check timing and so on .. )
If you want, you can check power report, but it is not closed to final number because lacking of clock cells and optimization cells.
Actully I want know that how we can say after see which which reports, say i have done synthesis and this netlist, we can deliver to rest of the team like PD, or for LEC team
There is no report says "OK to release". You need to clarify what is your target of synthesis.
Basically, synthesis need to clean "0" clock latency timing and Formal verification. The rest of thing like cell counts, static power ... are not so important as this phase, but it is depended on your targets before doing synthesis.
There is no report says "OK to release". You need to clarify what is your target of synthesis.
Basically, synthesis need to clean "0" clock latency timing and Formal verification. The rest of thing like cell counts, static power ... are not so important as this phase, but it is depended on your targets before doing synthesis.
In General, if TIMING is MET for your targeted frequency, you are good to start with PnR. But you should also check the above points posted by "slutarius" and make sure you are OK with Area; FF count; Power; etc.