synthesizing vs simulation
Simulation is the stage where you verify the fucntionality of your design which is usually preferred with the help of waveform viewers. These waveforms help you interpret easily about the functionality and also checks for any setu/hold violations.
But, Simulation doesnt have any library file with it.. so if any kind of gate delay or such technology library related issues will not be evident.
Synthesis is the hardware level implementation of the design. When this is done then you will involve the technolgy files and libraries. Thus any setup/hold violations here mean they need to be fixed but the same violations in the simulation level need not be fixed as they may not be the case after synthesis.
Another imp point is when you see the report generated by synthesis tool which is know as netlist you can actually trace the path of the design and fugure how you code has been implemented.. some tools shw the same on their GUI also.
I hope this helps you...
haneet