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Synthesis VS Simulation - explanation needed

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hayaloo

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synthesis vs simulaton

Hi all

I recently started to learn VHDL as i needed for my project but i still do not undestand the dofference between designs for synthesis and simulation could some one please help me with this matter .
thanks for your time
 

Tan

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synthesis and simulation

hayaloo said:
Hi all

I recently started to learn VHDL as i needed for my project but i still do not undestand the dofference between designs for synthesis and simulation could some one please help me with this matter .
thanks for your time

Hi,
Synthesis and simulation are two main terms used in vlsi design.Synthesis is used to create the netlist for the VHDL code you wrote for a particular application.You can see the hardware generated for the application written.After synthesis you can implement,place and route and dump the code into fpga's.

Coming to simulation.
Simulation is used to check the design with reference to timing.You can analysie the written code through wave forms.This is just a visual checking.Here you cannot download the code into fpga

I hope i am clear.
 

    hayaloo

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haneet

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synthesizing vs simulation

Simulation is the stage where you verify the fucntionality of your design which is usually preferred with the help of waveform viewers. These waveforms help you interpret easily about the functionality and also checks for any setu/hold violations.
But, Simulation doesnt have any library file with it.. so if any kind of gate delay or such technology library related issues will not be evident.

Synthesis is the hardware level implementation of the design. When this is done then you will involve the technolgy files and libraries. Thus any setup/hold violations here mean they need to be fixed but the same violations in the simulation level need not be fixed as they may not be the case after synthesis.
Another imp point is when you see the report generated by synthesis tool which is know as netlist you can actually trace the path of the design and fugure how you code has been implemented.. some tools shw the same on their GUI also.

I hope this helps you...

haneet
 

    hayaloo

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hayaloo

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synthesis vs simulation

thanks a lot guys now its clear for me
 

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