First of all I don't think it's an absolute must to use virtual clocks. It'll depend on the kind of methodology followed by the organization.
One example I can think of is, imagine you have signals belonging to multiple clock domains going to the pads; or maybe its the same signal which is driven by clock from the output of a clock mux. So virtual clock gives you the flexibility in this case to constrain the input and output delays based on individual clock frequencies.
Say sigA is driven by clock output from a clock mux who has ClkA and ClkB as input clocks. So you define two virtual clocks each synchronous to ClkA and ClkB respectively and write the input/output delay constraint which respect to each clock.
So this is cleaner than specifying a min/max delay constraint since this I believe will be less pessimistic. I hope it makes some sense.
As far as I know, a Virtual Clock cannot be attached to any port/net (otherwise it will become functional, not virtual). So, how can I define it to be synchronous to ClkA/ClkB?
So this will help the tool to time the path from sigA ( working on ClkA and going out ) to the ports w.r.t a virtual_ClkA, which is considered external to your chip but synchronous to ClkA.
If ClkA and ClkB are going out of the chip then you may use them for constraining the input and output delay. But you need virtual clocks when this is not the case.
Here's a link that explains the concept of virtual clocks and I guess it best answers your query --> Cadence forum
Why? They have different frequencies and probably different skews... What's about a clock divider by 4/5?
Should the source and divided clock be considered as parts of the same clock domain (where a maximum skew of clock edges is guarantied)?
How clock domains are defined? Let's say, should the source and divided by 2 clocks be defined as the same clock domain? What's about a clock divider by 3/5?
Why? They have different frequencies and probably different skews... What's about a clock divider by 4/5?
Should the source and divided clock be considered as parts of the same clock domain (where a maximum skew of clock edges is guarantied)?
Yes you are right, there can't be a generalization. Its up to the designer whether you want to put the divided clocks in the same group or not.
If you want to balance the divided and the source clocks then define them in the same group, otherwise don't.
Say, for example if the divided clock signals are not interacting with the source clock signals you may want to put them in different groups so that the tool doesn't spend time trying to balance them.