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[Synthesis] Virtual Clocks usage -> simple example

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ivlsi

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Hi All,

Can anyone provide a simple example how to use Virtual Clocks for Synthesis / STA?

When do we MUST use Virtual Clocks?

Thank you!
 

sharath666

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One scenario is when you have to specify input and output delays for ports which are not driven from a clock.
 

ivlsi

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So, why not to use MIN/MAX delays instead of Virtual Clock?

When usage of Virtual Clock is MUST?
 

harpv

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First of all I don't think it's an absolute must to use virtual clocks. It'll depend on the kind of methodology followed by the organization.

One example I can think of is, imagine you have signals belonging to multiple clock domains going to the pads; or maybe its the same signal which is driven by clock from the output of a clock mux. So virtual clock gives you the flexibility in this case to constrain the input and output delays based on individual clock frequencies.

Say sigA is driven by clock output from a clock mux who has ClkA and ClkB as input clocks. So you define two virtual clocks each synchronous to ClkA and ClkB respectively and write the input/output delay constraint which respect to each clock.

So this is cleaner than specifying a min/max delay constraint since this I believe will be less pessimistic. I hope it makes some sense.
 
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ivlsi

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define two virtual clocks each synchronous to ClkA and ClkB respectively
As far as I know, a Virtual Clock cannot be attached to any port/net (otherwise it will become functional, not virtual). So, how can I define it to be synchronous to ClkA/ClkB?
 

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using set_clock_groups and grouping the virtual_ClkA and ClkA in the same group.

set_clock_groups -group {ClkA virtual_ClkA}
So this will help the tool to time the path from sigA ( working on ClkA and going out ) to the ports w.r.t a virtual_ClkA, which is considered external to your chip but synchronous to ClkA.
 
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ivlsi

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Re: [Synthesis] Virtual Clocks usage -> simple example

As for divided clocks, should they be considered as synchronous and be defined in the same clocks group (using set_clock_groups command)?

- - - Updated - - -

define two virtual clocks each synchronous to ClkA and ClkB respectively and write the input/output delay constraint which respect to each clock
So, nevertheless why virtual clocks should be created? Why the constraints cannot be applied with relation to the ClkA and ClkB themselves?
 

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Re: [Synthesis] Virtual Clocks usage -> simple example

As for divided clocks, should they be considered as synchronous and be defined in the same clocks group (using set_clock_groups command)?
Yes, divided clocks should also be part of the same clock group.


So, nevertheless why virtual clocks should be created? Why the constraints cannot be applied with relation to the ClkA and ClkB themselves?
If ClkA and ClkB are going out of the chip then you may use them for constraining the input and output delay. But you need virtual clocks when this is not the case.

Here's a link that explains the concept of virtual clocks and I guess it best answers your query -->
Cadence forum
 

ivlsi

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divided clocks should also be part of the same clock group
Why? They have different frequencies and probably different skews... What's about a clock divider by 4/5?
Should the source and divided clock be considered as parts of the same clock domain (where a maximum skew of clock edges is guarantied)?
 

ivlsi

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[Moved]Clock Domains -> how defined?

Hi All,

How clock domains are defined? Let's say, should the source and divided by 2 clocks be defined as the same clock domain? What's about a clock divider by 3/5?

Thank you!
 
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ivlsi

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define two virtual clocks each synchronous to ClkA and ClkB respectively and write the input/output delay constraint which respect to each clock
So, nevertheless why virtual clocks should be created? Why the constraints cannot be applied with relation to the ClkA and ClkB themselves?
 

harpv

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Why? They have different frequencies and probably different skews... What's about a clock divider by 4/5?
Should the source and divided clock be considered as parts of the same clock domain (where a maximum skew of clock edges is guarantied)?
Yes you are right, there can't be a generalization. Its up to the designer whether you want to put the divided clocks in the same group or not.

If you want to balance the divided and the source clocks then define them in the same group, otherwise don't.

Say, for example if the divided clock signals are not interacting with the source clock signals you may want to put them in different groups so that the tool doesn't spend time trying to balance them.
 

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