My design consists of severa blocks. Upon synthesis, each block achieves a max speed 0f about 500 M on virtex 4.When I put the design all together, the max possible speed falls down to 300M.
Is this normal?Or does thismean i'mdoing something wrong..
yes. Usually if u dont give any constraints the synthesis tool will just like that will place and route the design. But if u give some contraints like if u give the clock frequency as a constriants, it will try to fit the design to satisfy the constraint.
If still u find any problem of slow clock you have to find out the longest path and u have to redesign such that u r delay is reduced.