Synthesis report doubts - the flip flop gate count

[energeticdin]

Synthesis report doubts

Hi,

Please clarify,

1. From the following synthesis area report, how can we find out the flip flop gate count .
Eg:


Number of ports: 601
Number of nets: 1387
Number of cells: 92
Number of references: 17

Combinational area: 85900.859375
Noncombinational area: 65242.964844
Net Interconnect area: 1863876.375000

Since non combinational will include, [Flipflop, latches, rams]
How to find only flip flop gate count.

Please let me know

2. Combinational area: 85900.859375
Noncombinational area: 65242.964844
Net Interconnect area: undefined.

Total area: Undefined.

What may be the reason. Why the area is undefined?

Whether library is not modeled properly

Dinesh

 

[jbeniston]

Synthesis report doubts

For q2 - you probably haven't set a wireload model.

 

[dcreddy1980]

Synthesis report doubts

You can generate from synopsys DC a detailed report about how many flip flops and what kind of flip flops are used in your design. With the above info, you can't really tell how many flip flops are present in your design. That would be pure guess.

If we would know that you dont have anylatches and RAM's, u can get the flip flip count by dividing the total non combinational area with basic flip flop area which will be available from the library.

May be u can use report_hierarchy command in DC.

Would like to hear more comments on this, if others have any new approach!!!

 

[energeticdin]

Re: Synthesis report doubts

Thanks a lot dcreddy1980 and jeniston


Dinesh

 

[energeticdin]

Re: Synthesis report doubts

Hi All,

One More query,

IF we are constraining area in Synthesis tool,
i.e set max area 0

Then what tool will do?

Whether tool put more effort to optimize area or increase run time?

What about tool effort?

Dinesh

 

[jaydip]

Synthesis report doubts

when you set max_area to 0, I guess tool will not put ANY effort to optimize an area .. tool will be free to take as much area as it can to meet timing requirements ..

 

[raju3295]

Synthesis report doubts

am sorry jaydip, i wont agree with u,,, generally we keep max area constraint 0 and also give timing constraint by specifiying clock period and i/o constraints,, in this way also tool will try to meet the timing and also it will perform optimizations to improve area nos

 

[vlsichipdesigner]

Re: Synthesis report doubts

hi,

to know the list of flip flop count just use this
sizeof_collection [all_registers]

question 2: regarding set_max_area 0
This is an area constraint you are giving to the tool, telling that i need an area optimized design, so tool would be working on the area effort also.

best regards,
chipdesign made easy
https://www.vlsichipdesign.com

 

[no_mad]

Synthesis report doubts

Hi,

Check this website:
https://asicdigitaldesign.wordpress.com/2008/08/24/max-area-0/

It really very informative and one of my fav ASIC's website. Enjoy.

-no_mad