Synthesis query regarding synchronisers !

[sakshi gupta]

How we inform to the synthesis tool while doing synthesis that two flops connected back to back in RTL is Synchronizer :?

 

[ebuddy]

Why do you need to inform the synthesis tool about the 2 flops?

 

[phoenixpavan]

Yes..even i think that its more of a t/c about which the synthesis tool need not worry of. So the synthesis tool will simply place a f/f according your design and need not worry whether it is synchronizing flip flop or not. Synchronizer is simply a name given to f/f's connected back to back without any combinational circuitry between them.For synchronization to work properly, the signal crossing a clock domain should pass from flip-flop in the original clock domain to the first flip-flop of the synchronizer without passing through any combinational logic between the two.

Since the discussion came...I heard that foundries provide special synchronizer cells to be used in asynchronous design. If that is the case maybe the tool automatically chooses these synchronizer cells whenever there is a data being transferred from clk1 domain to clk2 domain.

 

[sakshi gupta]

How synthesis tool will understand two flops connected back to back should be mapped to synchroniser cell or sync Flops from the library ?

Sakshi

 

[phoenixpavan]

Hi Sakshi,

Most of the cases a regular flip flop will serve the purpose...these synchronizer cells are used to be available in older libraries...I am not quite sure they are being provided with the libraries these days..Moreover these synchronizer cells are same as 2f/f back to back and placed very closely to each other to mininize the skew or a single f/f with a large gain..

Do you have any problem synthesizing ur design for CDC?

 

[ebuddy]

Usually one has no direct way to force synthesis tool to pick a particular cell, unless you instantiate that cell explicitly in your code.

 

[sakshi gupta]

Hi Sakshi,

Most of the cases a regular flip flop will serve the purpose...these synchronizer cells are used to be available in older libraries...I am not quite sure they are being provided with the libraries these days..Moreover these synchronizer cells are same as 2f/f back to back and placed very closely to each other to mininize the skew or a single f/f with a large gain..

Do you have any problem synthesizing ur design for CDC?

Thabks for the reply .currently we have sync flops in library that have good resolution time . How we make tool understand to pivck sync flops rather than normal flops ?

 

[paulki]

Hi,
I dont think while doing Synthesys we can constrain special purpose cell libraries (special sync flops), instead that is more appropriate while doing back-end PD activities (Timing closure and STA). What I meant to say that Sync Flop replacement is possible while doing PD. But LEC repetition is required here again.

-paulki

 

[VLSI_Designer]

Hi,

All the signal Cross overs from one clock domain to another clock domain, are to be well taken care of through RTL, if any specific synchronizer module provided in the library to be used and set a don't touch attribute on those cells while doing synthesis. I guess syntehsis tool like RC , or DC will not do any specific replacements of the synchronizers.
As, there are many synchronizer mechanisms like 2-flip-flop level synchronization, mux-enabled synchornization, pulse synchrnoizers ... the tool may not really understand the functionality of the cross overs....

Hope this helps