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Synthesis of 'z' in verilog.

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Feb 23, 2006
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I am writing verilog code for data compression techniques and I want to write 'z' in memory module. Also I would like to compare these 'z' values with logic 1 and logic 0. I know we can do it in simulation but what about synthesis. Can I do the same??? Is there any remedy to above problem.

Thank you,


No, I doubt a memory module will store a 'z' value. That would be a bad idea.

comapring with Z not possible in hardware.. so redesign your logic..

"Z" is called as high-impedance. In electrical world, high-impedance means open pin/connection. I hope you have got this concept here.
Okay now let's think! if you want to store "Z" in memory. That mean keeping your data input pins of memory open right? Its similar like if you want to store 1 you put 1 on data input. Now to store "Z" you have to make data input port open. Now its obvious that if you leave data input port open, the memory won't store anything.

Since there is not actual value as "Z" in digital logic like logic "0" or logic "1". In verilog its defined because to represent open connections. The "Z" factor is also used in dual direction buses. The high-impedence buffer output will be "Z" if disabled.


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'z' can not happen in real circuit!!

z is not a valid value for memory elements. z can be driven using tri state bufferes but memory element can not be driven high impedance.

a excellent coding style don't use any "z" in the design, except the iopad.
embedded the 'Z' state shall bring some trouble suah as testable, power....

Two scenarios may have z's, which are casez/x or assign statements.
For the previous one, it means that the corresponding z represents ignored.
However, for the latter, it is always used to model the three-state component as wished. For example, the bi-direction ports.

Note: please don't contain such bi-direction signals in your internal logic description. They are often used in your I/O description.


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