How can I check synthesis clock?

[coshy]

After, My colleague had finished synthesis task within Zero wire model, I'm trying to check whether synthesis was correctly done. Of course, I can check the synthesis script from him, but I want to use other way to check if I can.

How can I check synthesis clock instead of checking the synthesis script?

 

[brucesilver]

You can check the synthesized clock by looking at the post-synthesis netlist and constraints. Try running a timing report (like report_timing in Synopsys Design Compiler) to see if the clock tree and constraints match expectations. Also, you can check the clock definitions in the synthesized design using report_clock. Another way is to inspect the SDC (Synopsys Design Constraints) file used during synthesis to ensure the clock was correctly defined. If there are mismatches or unexpected results, the synthesis might not have been done correctly!

 

[ThisIsNotSam]

clock information is not present on the netlist, at least not directly. You would have to reload the netlist within your synthesis tool but doing no mapping or optimizations, using the same constraints, and see if if passes timing.

 

[sky_siliconthink]

After, My colleague had finished synthesis task within Zero wire model, I'm trying to check whether synthesis was correctly done. Of course, I can check the synthesis script from him, but I want to use other way to check if I can.

How can I check synthesis clock instead of checking the synthesis script?

Another double check method: run gate level simualtion with cell delay back annotated.

For STA timing and DC synthesis, you can refer to: https://www.udemy.com/course/digita...-synthesis/?referralCode=F99007C1E5B740E11E03