synthesis multiple modules in Xilinx WebPack

[cyboman]

i'm relatively new to Digital Design and still learning it.

i have a very basic 4 bit adder which i'm trying to synthesize. the adder has other modules included into it. the code looks something like this

`ifndef ADDER4TOP_V
`define ADDER4TOP_V

`timescale 1 ns / 1 ps

`include "adder4.v"
`include "hex7segc.v"
`include "clkdiv.v"

module adder4_top (
	output wire [3:0] an,
	output wire [6:0] a_to_g,
	input wire [7:0] sw,
	input wire mclk,
	input wire [3:3] btn);
	
	wire cout;
	wire [15:0] digit;
	wire clk_out;
	wire [3:0] s;

	assign digit = {{10{1'b0}}, cout, s};
	
	adder4 u0 (
		.a(sw[7:4]),
		.b(sw[3:0]),
		.s(s),
		.cin(1'b0),
		.cout(cout)
	);
	
	hex7segc u1 (
		.digit(digit),
		.clk(clk_out),
		.clr(btn[3:3]),
		.an(an),
		.a_to_g(a_to_g)
	);
	
	clkdiv #(.WIDTH(15)) u2 (
		.clk(mclk),
		.clr(btn[3:3]),
		.clk_out(clk_out)
	);

endmodule		 

`endif /* ADDER4TOP_V */

after i run the synthesis i get the following hdl report.

=========================================================================
* HDL Compilation *
=========================================================================
Compiling verilog file "..\src\halfadd.v" in library fulladd
Compiling verilog file "..\src\fulladd.v" in library fulladd
Compiling verilog include file "..\src/halfadd.v"
Module <halfadd> compiled
Compiling verilog file "..\src\adder4.v" in library fulladd
Compiling verilog include file "fulladd.v"
Module <fulladd> compiled
ERROR:HDLCompilers:27 - "fulladd.v" line 37 Illegal redeclaration of 'fulladd'
Module <fulladd> compiled
Module <glbl> compiled
Compiling verilog file "..\src\clkdiv.v" in library fulladd
Module <adder4> compiled
Compiling verilog file "..\src\hex7segc.v" in library fulladd
Compiling verilog include file "..\src/counter.v"
Module <clkdiv> compiled
Compiling verilog include file "..\src/mux41.v"
Module <counter> compiled
Compiling verilog include file "..\src/hex7seg.v"
Module <mux41> compiled
Module <hex7seg> compiled
Compiling verilog file "..\src\counter.v" in library fulladd
Compiling verilog file "..\src\mux41.v" in library fulladd
Compiling verilog file "..\src\hex7seg.v" in library fulladd
Compiling verilog file "..\src\adder4_top.v" in library fulladd
Compiling verilog include file "..\src/adder4.v"
Compiling verilog include file "..\src/hex7segc.v"
Compiling verilog include file "..\src/clkdiv.v"
Module <hex7segc> compiled
Module <adder4_top> compiled
Analysis of file <"adder4_top.prj"> failed.
-->

Total memory usage is 130264 kilobytes

Number of errors : 1 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

INFO:NetListWriters:633 - The generated Verilog netlist contains Xilinx UNISIM
simulation primitives and has to be used with UNISIM simulation library for
correct compilation and simulation.
Synthesis finished with errors.

the reason i used `include statements is for compilation purposes. right now if one of my modules uses another module i have to compile every module before i compile the top level one. i have recently read that i can use `include to get around that problem however the synthesizer seems doesn't recognize that.

i understand why the error is generated. the synthesizer thinks that fulladd.v is included twice, however i did look through the code and i don't `include fulladd.v twice. it seems like that synthesizer ignores `ifdef, `endif, and `include. does anybody know how to solve this problem?

basically what i want is to synthesize one single module when it has other modules included into it.

any help and insights are appreciated

 

[kamalkundu]

Hello,

I am facing exactly same problem. Please let me know how you solved this in your case.

Thanks.

 

[Jack// ani]

the reason i used `include statements is for compilation purposes. right now if one of my modules uses another module i have to compile every module before i compile the top level one. i have recently read that i can use `include to get around that problem however the synthesizer seems doesn't recognize that.

If you only compile your top level design, which has all dependencies instantiated in it , I don't think you have to individually compile all dependencies/module.

ISE is smart enough to handle this, so I see no point is using include directive here.

 

[cyboman]

ISE is smart enough to handle this, so I see no point is using include directive here.

that happens if your source files are in the same directory as your top level. if my sources are in different directory i need to include the files.

so the question still stands, what should i do if i want to use modules which are located in different directory than the top level?

 

[Jack// ani]

ISE is smart enough to handle this, so I see no point is using include directive here.

that happens if your source files are in the same directory as your top level. if my sources are in different directory i need to include the files.

so the question still stands, what should i do if i want to use modules which are located in different directory than the top level?

Ah...now I see what you're after!!

Its quite usual to have all related files in the same folder, so I didn't face this issue so far. It would be interesting to know how to make it work.

 

[mgray]

Hi cyboman,

If you post a link to your source files, I can try it in my Xilinx Webpack environment.

Thanks,
mike

 

[cyboman]

mgray,

i'll post my code today or tomorrow. thanks for looking into the issue.

 

[mrflibble]

Hello cyboman,

I just did a quick test in ISE 11 using and got it to compile from different subdirs.

testproject/src/top.v
testproject/src/a/b/test1.v
testproject/src2/test2.v

And in top.v I could instantiate them by just these 2 lines. No need to use `include.

test1 t1(.sys_clk(sys_clk), .a(clk_counter[19]), .b(clk_counter[18]), .sum_out(sum_out) );

test2 t2(.sys_clk(sys_clk), .a(clk_counter[19]), .b(clk_counter[18]), .xor_out(xor_out) );

As Jack// ani said, ISE will take care of that for you. Of course you do have to add ALL the .v files to the project in the project navigator, not just the toplevel source file.

 

[cyboman]

mrflibble,

thanks for the help.