synthesis: is my code fully RTL?

[arbalez]

if i can synthesized my design code without any error. does it mean that i had written 100% RTL code? in other words, is the code that can be synthesized can be considered 100% RTL?

i'm asking this because my gate-level simulation failed to show any positive result.

 

[wadaye]

Hi arbalez,

If you can synthsize your code without any Error, you can say that code is RTL. In

fact, we don't care about whether this code is RTL or not, we only care about whether

is can be synthsized.

 

[xysafety]

hi,
synthesizable is different from the verified.
When a code is synthesizable, it means it is just written in a RTL.
but it doesn't demostrate its function right.

 

[cmos_dude]

Hi
Your gate level simulation failed because your code, though an RTL, had the wrong functionality.
You need to check your RTL for the errors and then Resynthesize & Resimulate the Gate level Netlist to check for the correct results.

Rgds
CMOS Dude

 

[arbalez]

i understood now. so successful synthesis doesn't mean that it will function as it supposed to be right?

in the end, i need to change the code. that's sure a lot of work i wish myself can think in hardware.

thanks all.

 

[z81203]

before synthesis, you just need verify your code from functionality.
after synthesis, you must verify your netlist with function & timing.

 

[avimit]

Just being able to synthesize a code does not mean that its going to work after synthesis or on silicon. There are many things you want to take care of:
for example: A combinational feedback if present is not an error for the synthesis tool, but it wont give desired output after synthesis
another example is: unwanted latches: if rtl is not written properly, there wil be some unexpected 'latches' in the post synthesis design and the results will not be correct on a simulation run on post synthesis netlist.
There can be several examples like that:
So think, what your rtl be possibly mapped to after synthesis, before writing RTL
Kr,
Aviral Mittal

 

[beckchm]

Synthesis is a step in the digital design . The code that is synthesizable may meet some problems in the P&R and post-simulation.
So you must correlate the following work.

 

[arbalez]

do you mean here that the code of the pre-synthesis (functional/behavioral) is usually not the final code?
and the post-synthesis modification of RTL code is usually the final code of a design (that is guaranteed to work even if we do functional/behavioral simulation),

 

[anjali]

sometimes we may required to change the RTL even after layout. this is required to enhance fhe functionality or because of poor verification at RTL stage, synthesis stage etc..

This process is known as ECO. its too cost.

 

[avimit]

Well, the code of pre-synthesis is the final code, once the design meets specs. But if you go to PnR and the find a problem in the design, you have to come back from the PnR step, and fix your pre-synthesis code(RTL), synthesize it again, PnR it again. In some cases if the porblem is not a major one, the post-synthesis code i.e 'netlist' may be changed and only PnR is done again. In some very rare cases, if the problem is even more simpler to fix, it might then be fixed at the layout mask level, so that you dont have to do even th PnR again. But it all depends upon the change/fix that is required.
In summary, the pre-synthesis is the final code but it may or may not correpond exactly to the layout if some post synthesis fixes i.e ECOs have been done.
Kr
Aviral Mittal.

 

[zhanch]

I am afraid you can say in that way. You should check whether the synthesis tools can generate the circuits what you want to design.

 

[sxqzj]

It's not very important whether your code are RTL ones;instead you should verify your code from functionality before synthesis and verify netlist with function & timing after synthesis!

 

[anan_tv]

Haiii all,

On summary , it is just like as:

Design Entry (HDL code) ---> Simulation (Functional ) -----> Synthesis (Logical or Physical) -----> P&R--->Gate level Functional & Timing verification ---> RTL changes(optional) Back Annotation----> Tapeout.

Correct me if any wrong