Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Synthesis for Low Power

Status
Not open for further replies.

ivlsi

Advanced Member level 3
Joined
Feb 17, 2012
Messages
879
Helped
17
Reputation
32
Reaction score
16
Trophy points
1,298
Activity points
6,806
Hi All,

What special should be done for Low Power Synthesis?

Thank you!
 

englishdogg

Full Member level 5
Joined
Jan 10, 2012
Messages
250
Helped
38
Reputation
76
Reaction score
39
Trophy points
1,308
Location
India
Activity points
2,742
the question is way to high level to have a precise answer - first which power leakage or dynamic
some optimizations / tricks mentioned below
- Clock Gating
- Annotating activity during synthesis
- MultiVt Synthesis
- use CPF / UPF to achieve more savings depending on design architecture and application for eg Power Shut Off

-- ed
 
Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top