Synthesis for Low Power

[ivlsi]

Hi All,

What special should be done for Low Power Synthesis?

Thank you!

 

[englishdogg]

the question is way to high level to have a precise answer - first which power leakage or dynamic
some optimizations / tricks mentioned below
- Clock Gating
- Annotating activity during synthesis
- MultiVt Synthesis
- use CPF / UPF to achieve more savings depending on design architecture and application for eg Power Shut Off

-- ed