Dear all. Could anyone please tell me what kind of informations of the design do we need when we want to start a synthesis for a design? Or to start writing a script for the synthesis?
Thank you very much! :roll:
Dear all. Could anyone please tell me what kind of informations of the design do we need when we want to start a synthesis for a design? Or to start writing a script for the synthesis?
Thank you very much! :roll:
I am going to design for Asic.
I learn GUI now and try to start with writing my own script to get the timing report.
I need to know based on what informations i can constraint the path in the design
If you use synopsys, the easy way is that
you see 'command.log' after running design analyzer.
command.log records all commands you commanded in design compiler.
Hi, asimosc
I think the best way to master the tools is just to try it. And see manual .And the book mention above is OK, but just version is old and not include tcl scripts. It's a pity.
All mature companies use scripts to automate and standarize their
flow. Most senior asic engineers hve some script templates
in their disks. Just ask your colleagues, you will find it's preety easy.
Some web sites also have TCL scripts for downloading, try it....
Perhaps the fastest and easy start is using GUIs.
But scripts are much more powerfull and easy to learn. TCL is almost an standard for these kind of tools. You can find a lot of tutorials, reference programs and lots of docs at:
Dear all. Could anyone please tell me what kind of informations of the design do we need when we want to start a synthesis for a design? Or to start writing a script for the synthesis?
Thank you very much! :roll: