synthesis for a design - what info do I need?

[sonata]

to start synthesis

Dear all. Could anyone please tell me what kind of informations of the design do we need when we want to start a synthesis for a design? Or to start writing a script for the synthesis?
Thank you very much! :roll:

 

[Laplace]

Are you designing FPGA or ASIC?

 

[CatKing]

script is not a good starting.
try do a tutorial with any soft you have.

 

[jiang]

GUI tools is recommanded.
synthesis script is not easy for a newbie.

 

[always@smart]

Re: to start synthesis

Dear all. Could anyone please tell me what kind of informations of the design do we need when we want to start a synthesis for a design? Or to start writing a script for the synthesis?
Thank you very much! :roll:

-------------------------------------------------------------

There is a good book teaching you how to synthesis the RTL code using DC and PT and had been uploaded in the following link,hope it helps you.

**broken link removed**

Best Regards

 

[sonata]

I am going to design for Asic.
I learn GUI now and try to start with writing my own script to get the timing report.
I need to know based on what informations i can constraint the path in the design

 

[jiang]

If you use synopsys, the easy way is that
you see 'command.log' after running design analyzer.
command.log records all commands you commanded in design compiler.

 

[ljkong]

yeah.
many software have a log file to log the commands you have used.
maybe the name is different. but all is .log.
good luck

 

[linuxluo]

Hi, asimosc
I think the best way to master the tools is just to try it. And see manual .And the book mention above is OK, but just version is old and not include tcl scripts. It's a pity.

 

[ttspice]

Use TCL for DC....

All mature companies use scripts to automate and standarize their
flow. Most senior asic engineers hve some script templates
in their disks. Just ask your colleagues, you will find it's preety easy.
Some web sites also have TCL scripts for downloading, try it....

 

[fivaro1]

Perhaps the fastest and easy start is using GUIs.
But scripts are much more powerfull and easy to learn. TCL is almost an standard for these kind of tools. You can find a lot of tutorials, reference programs and lots of docs at:

dev.scriptics.c0m
http://mini.net/cgi-bin/wikit/

Regards

 

[debussy1765]

to start synthesis

1. library
2. tool which you want to use
3. language interface (tcl, vendor-language)
4. write script

 

[AndyJing]

Re: to start synthesis

i want to know how many engineer use tcl script or dc shell script ?
i like tcl,tcl is popular in eda domain.

 

[gaonkc]

to start synthesis

Now many company use tcl script.
TCL is a useful for ic design

 

[robin_su]

Re: to start synthesis

I think tcl is more popular than dcsh!

 

[francide]

Re: to start synthesis

1) clocks : root, frequency, paths (excluded FF, preserved trees etc.)
2) exceptions (false paths, multicycles)
3) boundary conditions (load, input transitions)

 

[allanweee]

to start synthesis

i also suggest learning the TCL mode.

 

[tom123]

Re: to start synthesis

you should determine following factors:

1) how many clocks in the design;

2) operating frequency requirement;

3) what is the foundry and process;

Dear all. Could anyone please tell me what kind of informations of the design do we need when we want to start a synthesis for a design? Or to start writing a script for the synthesis?
Thank you very much! :roll:

 

[realtek]

to start synthesis

try use DV(design vision),
1.set library path( wireload, ...)
2.open design_vision
3.read file
4. select clock (for constrain)
5. constrain
6. compile

the detail you can read SOLD!
(design_vision tutorial)