ya_montazar
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hi,
I want to synthesize a VHDL code by ISE ,but it generated an error:
"Signal to_uart cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release."
what's wrong with it???:roll:
I want to synthesize a VHDL code by ISE ,but it generated an error:
"Signal to_uart cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release."
Code:
process(rx_ready , start_frame_tmp)
variable i : integer range 10 downto 0 := 0;
begin
i_sig <= conv_std_logic_vector(i,4);
case i is
when 0 =>
start_frame_tmp <= '1';
end_frame_tmp <= '0';
when 9 =>
start_frame_tmp <= '0';
end_frame_tmp <= '1';
when others =>
start_frame_tmp <= '0';
end_frame_tmp <= '0';
end case;
if(start_frame_tmp = '1')then
to_uart <= character_pos( data_tmp(0) );
end if;
if(rising_edge(rx_ready))then
if(i /= 9)then
i := i + 1;
to_uart <= character_pos( data_tmp(i) );
else
i := 0;
end if;
end if;
end process;