Synthesis Constraints.

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e-bedlam

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Can some one help me to define SDC constraints on the output of the MUX (at the extreme end.)
If i give :
clock_generated_clock -source CLK -divide_by 1 [get_ports o_mux]
then the sequential path is left out but if i give :
clock_generated_clock -source CLK -divide_by 2 [get_ports o_mux]
then the combo path is left out from being constrained by the tool.

So how do i constrain both the paths.
Are we allowed to to put two clocks on the output of the mux. I mean can we mention both of the above constraints.

Thanks in advance.
 
Last edited:

Hi,

A little strange for the input of the FF. It should have input connection. Otherwise,
the format of the generated clock won't be known. From your constraints, suppose,
you need a 1/2 clock. It then similar to a circuit in the attached file, I think.


Peter
 

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Hi Peter , You are correct.
In your diagram also how do you constrain the o_MUX.

I am not using Synopsis DC/PT so -add option is not available.
 

Question: between clk pin and the output of your right end mux, there is only one flop? if yes, no create_clock are needed!
Personnaly, I will only declare one clock from TESTCLK.
 

Hi e-bedIam,

> create_clock -name CLK -period 10 -waveform 0 5 [get_pins DFF instance name/CLK]
> set_case_analysis 0 [get_pins [MUX instance name/SEL]

Or, directly
>create_clock -name CLK -period 10 -waveform 0 5 [get_pins DFF instance name/CLK]
>create_generated_clock -source CLK -name o_mux -divide by 2 [get_pins MUX instance name/Y]


Peter
 

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