tariq786
Advanced Member level 2
Synthesis Constraints
I am slightly confused about period constraints?
I am in the design exploration phase. I don't know what is the highest clock frequency my design can work with.
How do i quickly find out such details in the FPGA design flow? And once i find out such details, do i have to write constraint file?
Please help precisely
I am slightly confused about period constraints?
I am in the design exploration phase. I don't know what is the highest clock frequency my design can work with.
How do i quickly find out such details in the FPGA design flow? And once i find out such details, do i have to write constraint file?
Please help precisely