kuntul
Newbie level 6
I have written a mips pipelined datapath using verilog and then it does what it's supposed to do on simulation (ISim), however when I run synthesis and put it on my FPGA board it behaves differently. I have a branch instruction which branches when it's not supposed to, however on simulation everything runs seamlessly. What should I do if I encounter such experience?? I am frustrated now as I don't know how to resolve this.... Can this be because of sensitivity list, which causes the FPGA to behave differently? I have a branch forwarding unit, which looks like the following:
Code:
module BranchForwardingUnit(Clk, IDEXrd, IFIDrs, IFIDrt, IDEXRegWrite, ForwardC, ForwardD );
input Clk;
input [4:0] IFIDrs, IFIDrt, IDEXrd;
input IDEXRegWrite;
output reg [1:0] ForwardC, ForwardD;
initial begin
ForwardC = 0;
ForwardD = 0;
end
always @(IDEXrd, IFIDrs, IFIDrt, IDEXRegWrite) begin
ForwardC = 0;
ForwardD = 0;
//EX Hazard
if (IDEXRegWrite == 1)
if (IDEXrd != 0)
if (IDEXrd == IFIDrs)
ForwardC = 2'b10;
else if (IDEXrd == IFIDrt)
ForwardD = 2'b10;
endmodule