syntheses error VHDL - xilinx spartan3

[farnaz_j]

Hi
I'm coding a hexa port RAM using an IP Core generated module "dual port RAM". when I click the implement top module the synth process fails giving the error "ERROR:Xst:827 - "/myram/my_ram.vhd" line 137: Signal addrb_inp cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release."
It points to the line showing "process (CLK)".

my code is here:

architecture Behavioral of my_ram is

--INST_TAG
component  blk_mem_gen_v6_1
    PORT (
    clka : IN STD_LOGIC;
    ena : IN STD_LOGIC;
    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
    douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
    clkb : IN STD_LOGIC;
    enb : IN STD_LOGIC;
    web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
    addrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    dinb : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
    doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
  );
-- INST_TAG_END ------ End INSTANTIATION Template ------------
end component;

signal a_out_reg: STD_LOGIC_VECTOR (15 DOWNTO 0);
signal b_out_reg: STD_LOGIC_VECTOR (15 DOWNTO 0);
signal c_out_reg: STD_LOGIC_VECTOR (15 DOWNTO 0);
signal d_out_reg: STD_LOGIC_VECTOR (15 DOWNTO 0);
signal e_out_reg: STD_LOGIC_VECTOR (15 DOWNTO 0);
signal f_out_reg: STD_LOGIC_VECTOR (15 DOWNTO 0);
signal ena_inp : STD_LOGIC;
signal enb_inp : STD_LOGIC;
signal wea_inp : STD_LOGIC_VECTOR(0 DOWNTO 0);
signal web_inp : STD_LOGIC_VECTOR(0 DOWNTO 0);

signal addrb_inp : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal dinb_inp : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal doutb_inp : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal addra_inp : STD_LOGIC_VECTOR(3 DOWNTO 0);
signal dina_inp : STD_LOGIC_VECTOR(15 DOWNTO 0);
signal douta_inp : STD_LOGIC_VECTOR(15 DOWNTO 0);

shared variable count : integer := 0;
signal count_holder : integer := 0;

begin

inner_ram: blk_mem_gen_v6_1
port map(
 clka => CLKM,
    ena => ena_inp,
    wea => wea_inp,
    addra => addra_inp,
    dina => dina_inp,
    douta => douta_inp,
    clkb => CLKM,
    enb => enb_inp,
    web => web_inp,
    addrb => addrb_inp,
    dinb => dinb_inp,
    doutb => doutb_inp
);

process (CLK)
begin
count := count_holder;
if (count = 0 ) then
 if (CLK'event and CLK ='1') then
			if (ENA = '1') then
				ena_inp <= '1';
			
					if (WEA = '1') then
						addra_inp <=  ADDRA;
						wea_inp <= conv_std_logic_vector(1, 1);
						dina_inp <= DIA;
					end if;
				
				a_out_reg <= douta_inp;
			end if;
		
	elsif (CLK'event and CLK = '0') then
			if (ENB = '1') then
				enb_inp <= '1';
			
					if (WEB = '1') then
						addrb_inp <=  ADDRB;
						web_inp <= conv_std_logic_vector(1, 1);
						dinb_inp <= DIB;
					end if;
				
				b_out_reg <= doutb_inp;
			end if;
	end if;
		
		count := count + 1;
		
		
elsif (count = 1) then

if (CLK'event and CLK ='1') then
			if (ENC = '1') then
				ena_inp <= '1';
			
					if (WEC = '1') then
						addra_inp <=  ADDRC;
						wea_inp <= conv_std_logic_vector(1, 1);
						dina_inp <= DIC; 
					end if;
				
				c_out_reg <= douta_inp;
			end if;
		
elsif (CLK'event and CLK = '0') then
			if (EN_D = '1') then
				enb_inp <= '1';
			
					if (WED = '1') then
						addrb_inp <=  ADDRD;
						web_inp <= conv_std_logic_vector(1, 1);
						dinb_inp <= DID; 
					end if;
				
				d_out_reg <= doutb_inp;
			end if;
end if;
	count := count + 1;
	
	elsif (count = 2) then

if (CLK'event and CLK ='1') then
			if (ENE = '1') then
				ena_inp <= '1';
			
					if (WEE = '1') then
						addra_inp <=  ADDRE;
						wea_inp <= conv_std_logic_vector(1, 1);
						dina_inp <= DIE; 
					end if;
				
				e_out_reg <= douta_inp;
			end if;
		
	elsif (CLK'event and CLK = '0') then
			if (ENF = '1') then
				enb_inp <= '1';
			
					if (WEF = '1') then
						addrb_inp <=  ADDRF;
						web_inp <= conv_std_logic_vector(1, 1);
						dinb_inp <= DIF; 
					end if;
				
				f_out_reg <= doutb_inp;
			end if;
	end if;
	count := count + 1;
		
	elsif ( count = 3) then
		count := 0;
	
	end if;
	
	
	count_holder <= count;
	
	DOA <= a_out_reg;
	DOB <= b_out_reg;
	DOC <= c_out_reg;
	DOD <= d_out_reg;
	DOE <= e_out_reg;
	DOF <= f_out_reg;
	wea_inp <= conv_std_logic_vector(0, 1);
	web_inp <= conv_std_logic_vector(0, 1);
	ena_inp <= '0';
	enb_inp <= '0';

end process;
			


end Behavioral;

I've read the code over and over but I don't figure out what is wrong with it. can anybody plz help me?

 

[TrickyDicky]

An FPGA can only use a single clock edge per register - either the rising or falling. Not both.

 

[FvM]

I didn't check thoroughly, but it might be that specific registers are only used with either rising or falling edge clock. The overall "if count = xx else ..." structure around the clock sensitive condition doesn't comply with synchronous logic templates and must be reordered, placing the if clauses inside the clock sensitive code.

For clarity, I suggest to write separate processes with positive and negative clocked registers.