syntax error near process

[parallax18]

Good evening,

I need your help for one technical problem. I can't solve an error in my VHDL soft project because an error appears
at the line "end process;" which tells me " syntax error near process".

Thank you very much for your help!

 

[KlausST]

Hi,

Next time please upload code and error messages as text instead of big filesize pictures. Use code tags.
Text also enables text search.

Klaus

 

[parallax18]

Good evening Klaus,

I transmit you my vhd sources. Thanks for your help!

 

[FvM]

Review VHDL textbook about correct case statement syntax. Each case needs a matching end case.

--- Updated Feb 21, 2021 ---

case CMP is
    when 1 =>LED<= "1111001";
    when 2 =>LED<= "0100100";
    when 3 =>LED<= "0110000";
    when 4 =>LED<= "0011001";
    when 5 =>LED<= "0010010";
    when 6 =>LED<= "0000010";
    when 7 =>LED<= "1111000";
    when 8 =>LED<= "0000000";
    when 9 =>LED<= "0010000";
    when 0 =>LED<= "0000001";
    when others =>
end case;

 

[parallax18]

Hello Klaus,

Thank you very much for your answer. You are right according to my errors.
There was a problem with the "case when" syntax.