ibtesam90
Newbie level 6
Dear All,
I am trying to generate test patterns for a test bench circuit "wb_conmax" by opencores. I have successfully generated the gate-level netlist. And I had successfully inserted the scan chain. However, I am unable to generate test patterns. It gives following error
The script I am using to generate is as follows:
I unable to get any help on Solvnet or get any document on TestMax from Synopsys site.
Thanking in advance for you time and help.
Regards/
I am trying to generate test patterns for a test bench circuit "wb_conmax" by opencores. I have successfully generated the gate-level netlist. And I had successfully inserted the scan chain. However, I am unable to generate test patterns. It gives following error
The script I am using to generate is as follows:
Code:
read_netlist -library ../SAED90_EDK/SAED_EDK90nm/Digital_Standard_cell_Library/verilog/saed90nm.v
read_netlist report/wb_conmax_top_top_after_scan.v
run_build_model wb_conmax_top
add_slow_bidi -all
set_buses -external_z X
set_drc -allow_unstable_set_resets
set_drc -clock -dynamic -disturb_clock_grouping
set_drc -allow_unstable
run_drc report/wb_conmax_top_top_after_scan.spf
set_simulation -xclock_gives_xout
report_violation -all
set_faults -model stuck
add_faults -all
set_faults -fault_coverage -summary verbose -report uncollapsed
set_atpg -fill X
report_atpg_constraints
report_buses -all
report_clocks
report_pi_equivalences
report_settings
run_atpg -auto
write_patterns ./wb_conmax_full.stil -internal -format stil99 -replace
exitThanking in advance for you time and help.
Regards/