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Synopsys Primetime constraints issue

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fv

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prime time constraints

Hi Group,
I am a new user of Synopsys Primetime. I have a verilog design, on
which timing analysis is to be done. Now I am not aware of the maximum
register to register delay and so I do not understand as to what kind
of clock constraint should I apply. Can primetime analyse the design
and use a default clock or such if I dont give it one.


Thanks,
Fazela
 

joe2moon

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In order to do the static timing analysis(STA), clock definition is the minimum requirement.
Because in PrimeTime, most timing constraints are related to clock.
------------------------------------------------------------------------------------

So, you have to apply the following timing constraint to PT at least,
pt_shell> create_clock -name <clock name> -period <in ns> <clock port/pin>

Give the desired clock period for checking the timing of the netlist.

Then you can run
pt_shell> report_timing
to see the result.
------------------------------------------------------------------------------------
 

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