rui_yang
Newbie level 2
Hi all,
I used synopsys nanosim to simulate verilog netlist. The verilog netlist is generated from DC. But when I run the nanosim, the segmentation faults came out. What are these faults mean? How can I solve these??
Thanks for any help!!!
I used synopsys nanosim to simulate verilog netlist. The verilog netlist is generated from DC. But when I run the nanosim, the segmentation faults came out. What are these faults mean? How can I solve these??
Thanks for any help!!!