Synopsys Design Compiler not responding to set_load

[rijudg]

I am synthesizing some designs using my own custom cells. I am trying to see how different parameters like clock and load affect the synthesis and / or timing.
The issue is, no matter what I do to the set_load parameter, my synthesis never complains or never reports a SLACK violation. However, changing the clock period does change the SLACK as expected. Any ideas how to check if set_load is doing anything?

Here is the script I am executing:

# set TOP to the name of the module to be synthesized
set TOP "mealy"
set edifout_netlist_only "false"

# paths for libraries used in synthesis
set search_path [concat {. /opt/CDS/cadence2005/ic5141/tools.lnx86/dfII/etc/dci/synlibs} $search_path]



#set target_library [list "/home/kaushikd/Digital_Synthesis/dno/NangateOpenCellLibrary_PDKv1_3_v2010_12/Front_End/Liberty/NLDM/NangateOpenCellLibrary.db"]
#set link_library [list "/home/kaushikd/Digital_Synthesis/dno/NangateOpenCellLibrary_PDKv1_3_v2010_12/Front_End/Liberty/NLDM/NangateOpenCellLibrary.db"]


set target_library [list "/home/kaushikd/Digital_Synthesis/timing/ibm32lib.db"]
set link_library [list "/home/kaushikd/Digital_Synthesis/timing/ibm32lib.db"]





set CLKPERIOD "1"

#set target_library [list "/home/kaushikd/Digital_Synthesis/synth/reduced2_typical.db"]
#set link_library [list "/home/kaushikd/Digital_Synthesis/synth/reduced2_typical.db"]

# Read in the design
define_design_lib control -path ./CONTROL
analyze -work control -f vhdl ../vhdl/$TOP.vhdl
elaborate -lib control $TOP

# Define clock (period in ns)
create_clock clk -name clk -period $CLKPERIOD
set_propagated_clock clk

# Define output load (in pF)
set_load 10000000000000000 [all_outputs]
# Set the optimization constraints
set_max_area 0
set_max_dynamic_power 0

# Map and optimize the design
current_design $TOP
uniquify

set_flatten true -effort medium -minimize multiple_output -phase true

# Run synthesis
compile -ungroup_all -map_effort high -incremental_mapping

# Run lint on the design
check_design

# Create some reports
redirect [format "%s%s" $TOP ".area"] { report_area }
redirect [format "%s%s" $TOP ".power"] { report_power }
redirect [format "%s%s" $TOP ".timing"] { report_timing -max_paths 25 }
redirect [format "%s%s" $TOP ".clock"] { report_clock }

# write output
write -hierarchy -format vhdl -output [format "%s%s" $TOP ".vhdl"]
write -hierarchy -format ddc -output [format "%s%s" $TOP ".ddc"]

# write a design constraints file for use by Encounter
write_sdc [format "%s%s" $TOP ".sdc"]

 

[RCircuit]

If your cells have infinite driver capabilities, set_load would be useless.

 

[rijudg]

If your cells have infinite driver capabilities, set_load would be useless.

But my cells are custom small sized cells built in IBM 32nm and characterized by me using the Encounter Library Characterizer. Does this mean that during that characterization I messed up something?

What should I see when I increase set_load............do I see some slacks not being met (negative SLACK) or something else, like the synthesis failing?

 

[RCircuit]

You can set output delay, when load is higher, you should see timing violations.

 

[rca]

If you do not define any set_output_delay, there is no timing constraint on your outputs.
set_load is "required" to estimate the delay added by the last wire to check if the setup is respected versus the set_output_delay.

 

[rijudg]

If you do not define any set_output_delay, there is no timing constraint on your outputs.
set_load is "required" to estimate the delay added by the last wire to check if the setup is respected versus the set_output_delay.

Thanks! I was not setting output_delay and so no matter how much load capacitance I put in, the output delay requirement was always satisfied I think.
I put in a set_output_delay and now depending on the load capacitance, Design Vision complains about negative slack sometimes.