Synopsys - a doubt in finding the area of a design

[vivek_p]

Synopsys - area

I have a doubt in finding the area of a design using Synopsys Design Compiler:

1) using the command "report_area" after compilation, before creating the clock and setting clock constraints

2) using the command "report_area" after compilation, after creating the clock and setting clock constraints

When I found out the area using both the ways, I got different areas.......Can anyone tell me how this difference in area comes.

Which method should I follow to find the area of the design....................

 

[Syswip]

Re: Synopsys - area

Hi vivek_p,

Are you compiling your design without clock creation and without constraints?

Could you please clarify what did you mean:

1) using the command "report_area" after compilation, before creating the clock and setting clock constraints

2) using the command "report_area" after compilation, after creating the clock and setting clock constraints

Bests,
Tiksan

 

[vivek_p]

Re: Synopsys - area

Hi,

I have first compiled the design without creating the clock and setting the constraints. I checked the area and power after this process.


After tat I created a clock and set the constraints, and then found area and power.


There is difference in area.........is this because of insertion of clo0ck buffers or so.

Which area should I consider for comparison of designs (Area comparison)

 

[RBB]

Synopsys - area

I'd assume after you've set your constraints, design compiler will optimizing certain timing paths.
You should consider the 2nd area value.

 

[AdvaRes]

Re: Synopsys - area

Sure,
The second area is more realistic coz it takes into accound the area averhead due to buffers for exemple.

 

[Syswip]

Re: Synopsys - area

Hi vivek_p,

You should create clock and set constraints before compilation otherwise you'll have wrong results, area, power, timings...

Bests,
Tiksan

 

[sam536]

Re: Synopsys - area

The area numbers are obviously different. Even after defining the clock and constraints, the multiple synthes runs will produce not the same area and timing reports. The reason is simple,timing engines work differently..

Design compiler doesnt add clock tree(hope u have set set_dont_touch on clock N/W)..so thats not the root cause for your area increase...


What you expect from the tool to do without setting the constraints?. jst map and give the results. Its working on a project without setting the deadlines?.