gurki
Newbie level 1
Hello,
i currently evaluate the sysnopsys vcs mixed signal simulation tools. Everything works fine, there is lots of documentation and examples for VHDL, Verilog in Combination with Spice and VerilogA. There _is_ documentation for digital-only simulation of SystemC (which i managed to run just fine), but i could not find any documentation on how to combine SystemC with spice/veriloga.
Can anyone help me out with a link to some documentation or a "hello world" example?
i currently evaluate the sysnopsys vcs mixed signal simulation tools. Everything works fine, there is lots of documentation and examples for VHDL, Verilog in Combination with Spice and VerilogA. There _is_ documentation for digital-only simulation of SystemC (which i managed to run just fine), but i could not find any documentation on how to combine SystemC with spice/veriloga.
Can anyone help me out with a link to some documentation or a "hello world" example?