Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[synopsis vcs] Mixed signal simulation using SystemC and Spice/Veriloga

Status
Not open for further replies.

gurki

Newbie level 1
Joined
Aug 21, 2017
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
12
Hello,

i currently evaluate the sysnopsys vcs mixed signal simulation tools. Everything works fine, there is lots of documentation and examples for VHDL, Verilog in Combination with Spice and VerilogA. There _is_ documentation for digital-only simulation of SystemC (which i managed to run just fine), but i could not find any documentation on how to combine SystemC with spice/veriloga.

Can anyone help me out with a link to some documentation or a "hello world" example?
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top