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Synchronous FIFO with different input or output data width from memory width

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er.akhilkumar

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Hello All,

Has anyone got any information about a synchronous FIFO having input/output data width different from memory width implemented in FIFO?

For example:

Input data width: 16
Output data width : 32
Memory width : 32

Can we develop such type of FIFO?

Thanx
 

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