Well Asynchronous design is supposed to consume less power, its the main research goal for all asychronous vlsi design groups. They do have their share of problems.
In normal circuits you can combine both with proper interface logic, I guess.
The anser to the question is application specific. Anyhow to generalize, synchronous designs are more power hungry than asynchronous design. As the clock network consumes the major power in synchronous designs.
As other memebers have mentioned designing an purely asynchronous design is very challenging and for any information you may try googling to read the ongoing research work.
It may be the same in average power. But synchronous consume much larger power at clock rising or falling edge, which will lead to power integrity problem.