Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
The anser to the question is application specific. Anyhow to generalize, synchronous designs are more power hungry than asynchronous design. As the clock network consumes the major power in synchronous designs.
As other memebers have mentioned designing an purely asynchronous design is very challenging and for any information you may try googling to read the ongoing research work.