Synchronizing external signals

[Andrei Salahoru]

Hi,


There are two signals who must be taken in account. First is the status signal, and then is a N ms period signal, wich will increment a module later.

Now, every time the status is active, I have to check the local clock accuracy (?) according to N ms signal and synchronize the N ms signal to internal clock.
But when the status is low, I have to generate myself an N ms signal. This generated N ms signal will replace the external signal.

Does anyone has an idea how this module must be modeled?
And if the status signal is asynchronious, how do I keep in track how many ms are left untill the next rising edge? ( when the internal signal will replace the external, it has to be exactly at the same time. Also, the viceversa must be the same)

I will develop in Verilog, but the thing I want is the idea.

If I didn't explain well, please let me know.

Best regards,
Andrei Salahoru.

 

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( when the internal signal will replace the external, it has to be exactly at the same time. Also, the viceversa must be the same)

This requirement is impossible to meet.

Clock drift alone (as I doubt they are running off the same clock source) will result in a non-exact N ms edge (with respect to the external signal) when the internal signal is used.

 

[Andrei Salahoru]

This requirement is impossible to meet.

Clock drift alone (as I doubt they are running off the same clock source) will result in a non-exact N ms edge (with respect to the external signal) when the internal signal is used.

Ok. So let's say that my external signal has a period = 500 ms. It is running normally untill status will go low, and let's pretend that are 100 ms left untill next rising edge of external signal is met. In this case, I shall not take in account this signal and drive the internal signal to output of the module. But how do I do it? How do I obtain that exactly 100 ms in my internal signal, and after, to keep that 500 ms period, untill external signal is available again.

And again, lets pretend that external signal is active again when there are 50 ms left untill next rising edge.

 

[Andrei Salahoru]

There is something I have in mind.

When rising edge of N ms is met, I shall enable a frequency divider, that will output exact N ms (the value is known) and will be working in parallel with N ms signal.

The status signal will control a MUX block. When is HIGH, the block will drive the N ms signal. When is LOW, will drive internal generated signal (internal N ms signal).

What should I do when the external N ms signal will be active again? What if my internal signal will be at 60-70% of this period, and the external signal will arrive at 30 or 90%? My next modules will not receive the exact period to increment.

 

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you seem to be missing the point I made earlier.

Unless the clocks generating the external signal and the internal signal are frequency locked (or perhaps both being locked to some other external time standard, e.g. NIST ITS), you won't have an exact number of clock cycles to allow a seamlessly switch between the two.

If they are frequency locked then it's very easy to switch between the two with only a single clock cycle (assuming the frequency locked clock is faster) of slop.

 

[Andrei Salahoru]

Ok, I undertood.

Both signals are frequency locked. Is my idea about solving this good?

 

[Andrei Salahoru]

Internal clock will be generated using the board's frequency, wich is 100 MHz.

 

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If there is frequency lock between the external and internal versions of this signal, then there is no issue with...

external enabled, switch to internal (which is synchronized to the external in whatever fashion you use, counters etc), and finally switched back to external.

The only real problem will be with what is the system requirements for the following scenario...

start with internal (never synchronized to external), now switch to external... This can't be done without a "glitch" in the timing of the signal as they are unlikely to be in phase. Has this been specified or is it impossible to have the internal signal not synchronized with the external signal?

 

[Andrei Salahoru]

The deal is that the internal signal has to replace the external signal, in order to keep a clean clock for a later counter. ( it has to be exactly 1 s, because I have to extract the date (hh,mm,ss) from some frames and when the external is off, the frames are off and I have to keep counting untill the external is available again).

Switching between them is a problem for me, because I don't know when the external will go off or on, so is asynchronious.

 

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The deal is that the internal signal has to replace the external signal, in order to keep a clean clock for a later counter. ( it has to be exactly 1 s, because I have to extract the date (hh,mm,ss) from some frames and when the external is off, the frames are off and I have to keep counting untill the external is available again).

Switching between them is a problem for me, because I don't know when the external will go off or on, so is asynchronious.

Are you saying the switch has to be done based on the availability of the external signal? Or is it based on another signal? Even if it's based on the external signal only, you could conceivably have the internal one synchronized to the external (while there is an external one) then switch over when the external has been detected to not have occurred.

The options there are skip an entire external pulse (missing an entire rising edge), or immediately switch to the internal pulse (resulting in skew in that rising edge). Which one is used is entirely based on the requirements of the design.

 

[Warpspeed]

Seems to me you need a free running oscillator (software timer) that runs all the time and constantly drives the output.

When the external reference source is available, the free running oscillator is locked to the external reference. When not enabled, the the locking mechanism decouples and the oscillator continues to run on by itself.

Its really a phase locked loop with gated synchronisation. This type of thing is done all the time in hardware.
Like a pendulum or a flywheel, it just needs the occasional push to keep it precisely synchronised, but then runs on by itself until the next synchronisation.

 

[Andrei Salahoru]

There is a status signal wich flags every time I should use external or internal.

- - - Updated - - -

Here is the entire requirement*:

"Our block retrieves a xPPS signal generated by the an external module , which are synchronized data frames.
This signal of a frequency of 1 Hz , is used to determine the accuracy of the own system clock . For this, a counter counts the number of rising edges of our own clock during periods of xPPS signal to derive its stability.
When the Status signal is LOW, the xPPS signal is unreliable and should not be taken into account. A pseudo internal xPPS signal replaces the xPPS.
The block transfers the output signal xPPS_Sync and error quantified clean clock."


I've changed some names, but are not relevant for the moment.

Have you got an idea how should I do this in Verilog?