sorry
suquid but the picture tells me nothing of your requirements;
what's more I'm familiar with xilinx fpga architecture but have
no experience with them;
missing info is the range and step of phase shift you need;
[from your attached picture I guess you need to shift a clock signal
not a random pulse];
first - read carefully DCM description if and how you can shift
phase of the output clock, DCM looks for me as the easiest solution,
your reference clock can be an input to a DCM module, the DCM itself
works as a 'phase shifter' without changing the output frq.;
second - read in ise/virtex manual description of a dll module, such module,
from user point of view, is nothing more then just a delay line;
third - you can force P&R tool to place a specific cell where you want,
see floorplaning section on your tool manual, carefull floorplanig will
allow you to build a delay line as a series of cells the clock signal
has to travel throu and a multiplexer to select desired delay;
and last - if your delay tap can be as big as ~2ns you can use
the solution I've described in the previous post - scan your signal
with both slopes of a fastest clock allowed for your fpga, the scaning
clock you can produce with a DCM module;
where can I find VHDL codes for synchronizers (FIFO, Data Delay etc.)
as far as I know there are no vhdl/verilog codes for fifo, you need to
use tool specific macro [CoreGen in ise case, megawizard for quartus];
no idea what 'Data Delay' is although I guess you mean a kind of
shift register that shifts bytes instead of bits[what means a kind of fifo];
if I'm right such functionality you can build manually if you do not need all fifo features;