I have a devboard (with cyclone V) which gets 10bit data + clk(83Mhz),
The problem is that the clk is connected to a standard GPIO pin (not global), and no i don't have an option to reroute it.
How can i synchronize this data to second clk2 domain with the same freq.
I know there is a technique that i can synchronize this data with double/triple DFF, but how to connect the clk
I don't know about cycloneV but for Xilinx 7 series and above FPGAs there is an XDC command to be used when a normal GPIO pin carries a clock signal. Isn't there something similar with Altera/Intel?
If there is, then use that command in your SDC file. There might be timing problems, but can be resolved by proper analysis (using proper input/output delays or inst. a delay element in the data path).
How can i synchronize this data to second clk2 domain with the same freq.
I don't know about cycloneV but for Xilinx 7 series and above FPGAs there is an XDC command to be used when a normal GPIO pin carries a clock signal. Isn't there something similar with Altera/Intel?
A GPIO pin driving several register clocks will be automatically routed through a Cyclone V global clock network. But it can't be used as PLL reference clock.
The feature to route a GPIO to a clock network is also the prerequisite for using a DC (domain crossing) FIFO for the design problem.
You should use this technique only for single bit signals. But your signal is a 10bit data, so use a FIFO to sync.
If the data lines are known stable during a certain part of the clock cycle, the data can be consistently read in with a DFF synchronizer for the clock (and delaying DFFs for the data lines as far as required).