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Synchronising (interleaved) of 4 Boost PFCs?

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Advanced Member level 5
Jun 13, 2021
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Need to sync two UCC28070A’s, each with a 120kHz pulse train. Pulses should be 400ns to 600ns long. (don’t want much variation as max duty cycle depends on it).
The two 120kHz pulse trains should be in anti-phase to each other.
Can you think of any other ways than the attached “ocean” of componentry?
LTspice and JPEG scm attached.


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D flip-flop rotates incoming clock pulse to two staggered outputs. Choose type of logic gate depending on whether you want duty cycle range of 1-49 percent, or 51-99 percent. Omit the unused type.

Notice universal duty cycle change performed by a single voltage reference adjustment.

D FF logic gates send dual interleaved pulses 1-49 or 51-99.png
Thanks Brad, thats absolutely fantastic!!!.......i have implemented the ramp ganerator with a 555 as in the attached schem and LTspice.

In fact, since i dont need variable duty , i may just see if i can find a suitable high duty cycle pulse train generator to put into it......i think the ramp gen i put in here is a bit dodgy....the 555 may not in reality discharge down to zero volts...

I also think i'm putting too high spikes of discharge current into the 555...
--- Updated ---

Actually, i am aso beginning to wonder if i can put a high duty cycle osc through an inverter, and then feed it to this hi and lo side gate driver...?

...the thing is, most of these chips that do high duty cycle, do so with very poor tolerance.
--- Updated ---

I mean, the UCC2808 provides two anti phase pulse trains (each of 120kHz) would be easy to get them both on max duty cycle...but from part to part, that max duty could be very variable.



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Also, i think Brads excellent circuit might be done like the attached, just adjust RC of ucc28c43 to have a certain max duty cycle...i think the RC of UCC28C43 charges between 2.8V and 1v, with an 8.4mA discharge current.

The UCC28070A itself could give the hi duty cycle input, but its not clear how to make it "free run" what has to be done to the current sense input? has protections inside it which might disable it.


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Think this is the lowest comp count , and accurate way of doing 2 anti-phase pulse trains, each of frequency 120kHz....hi time, 400ns to 600ns...shame nothing off the shelf, but there you go.

Many thanks to Brad for the crucial Output stage.


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Since your topic mentions 4 converters, and since you want a long duty cycle more or less unchanging ...

There is the shift register method. Below a 4017 IC produces 4 output pulses which are non-overlapping. By referencing these to positive supply voltage you obtain four staggered overlapping pulses, 75 percent duty cycle.

Duty cycle can be changed to some degree by combining diodes at the outputs, skipping outputs, etc.

4017 rotates pulses 75 pct duty cycle 4 led's ref'd to 5V.png
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