Hi FvM,
Thanks.
The board is working much better now. I am not having any problems with the JTAG and the main problem with the design is more predictable now - i.e. its gotten considerably worse so at least now it looks like a VHDL error instead of hidden noise.
I've enclosed a shot of my scope during one write cycle. My uC has a max SPI word size of 11 bits so my program sends two which the CPLD is to treat as one.
The top trace is the SPI clock and the bottom is the CTS line.
The program running on the device is below.
With this program i've tried to make it behave as close as possible to my SPI design while removing the effects of external logic.
I also added a chip_enable line to try and elimate the affect of any spurious signals between transmissions, though there is nothing done to remove ringing if that is the problem yet.
Whats on the scope in the picture isn't always whats displayed; many times I wont see the CTS signal at all in the 22 clock cycles, sometimes its a very short pulse that could be mistaken for noise.
I chose the enclosed image because, looking at the code, if its synthesized correctly, shouldn't it be impossible to get that?
EDIT: Forgot to mention, I tried syncing everything to the main system clock within one process, and increasing the clock speed of the SPI to 66Mhz. Both times I got pretty much the same result as I am getting now.
EDIT: I just modified my uC code and cut the main system clock for the CPLD in half to ~35Mhz and it seems to be working. I can send the command that gives a visible result on the board continually and see it take affect in the main program, without the SPI slave 'losing its place'.
I am puzzled as to why this is, the timing analysis tool approved my design to run at 120Mhz, and the whole point was that the SPI functionality should be independant of this anyway.
Hopefully I can get it working at at least 50Mhz as this is the rate I would want ideally for my application, or, even better, figure out what the cause is :!:
Code:
Entity uC_Data_DeShifter IS
PORT(
serial_data_clock : IN STD_LOGIC;
serial_data_in : IN STD_LOGIC;
serial_clearToSend : OUT STD_LOGIC;
serial_chipenable : IN STD_LOGIC; --active low
Word : OUT STD_LOGIC_VECTOR(21 downto 0);
WordReady : OUT STD_LOGIC;
-- Clear : IN STD_LOGIC;
SyncSystemClock : IN STD_LOGIC
);
END uC_Data_DeShifter;
ARCHITECTURE main OF uC_Data_DeShifter IS
shared variable data_register : BIT_VECTOR(21 downto 0);
shared variable word_counter : integer range 0 to 21 := 0;
signal propagate : std_logic := '0';
signal Clear : std_logic;
BEGIN
recv_data : PROCESS( serial_data_clock, Clear )
BEGIN
if Clear = '1' and propagate = '1' then
serial_clearToSend <= '1';
propagate <= '0';
else
if serial_data_clock'event and serial_data_clock = '1'
and propagate = '0'
and serial_chipenable = '0'
then
serial_clearToSend <= '0';
if word_counter < 21 then
data_register(0) := to_bit(serial_data_in);
data_register := data_register sll 1;
word_counter := word_counter + 1;
else
data_register(0) := to_bit(serial_data_in);
Word <= to_stdlogicvector(data_register);
propagate <= '1';
word_counter := 0;
end if;
end if;
end if;
END PROCESS;
sync_proc : PROCESS( SyncSystemClock )
BEGIN
if SyncSystemClock'event and SyncSystemClock = '1' then
if propagate = '1' then
Clear <= '1';
else
Clear <= '0';
end if;
end if;
END PROCESS;
END main;