sync between clocks - interesting q

[yuvalkesi]

Hi,
I tried to search the forum, but didn't get an answer.
I have a process of 250MHz, of which 62.5MHz is created. I want to cancel it and use a PLL.
Since this is a working design, I need to 'blend in' without making a mess...
My problem is that in the current process of the making of the 62.5MHz clock, other control signals are used for other processes (those are in the 250MHz clock domain). So, I still need those signals and cannot delete them.
I need to make a PLL clock of 62.5MHz, but make those control signals (which are made of the 250MHz) synched with the new PLL clock in such way all will still work normally.
Any ideas?
Thx.

 

[FvM]

Generally speaking, you'll use synchronizers. Toggle synchronizers are particularly helpful when transiting from a fast to a slow domain.

 

[bking]

Lots of good info in this paper: http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf

 

[ads-ee]

Hi,
I tried to search the forum, but didn't get an answer.
I have a process of 250MHz, of which 62.5MHz is created. I want to cancel it and use a PLL.
Since this is a working design, I need to 'blend in' without making a mess...
My problem is that in the current process of the making of the 62.5MHz clock, other control signals are used for other processes (those are in the 250MHz clock domain). So, I still need those signals and cannot delete them.
I need to make a PLL clock of 62.5MHz, but make those control signals (which are made of the 250MHz) synched with the new PLL clock in such way all will still work normally.
Any ideas?
Thx.

Use the 250MHz clock as the input clock to the PLL. Generate both a 250 MHz 0 degree phase clock and a 62.5 MHz (250 divided by 4) 0 degree phase clock. Both of the clocks will be considered synchronous so you won't have to do anything special in both Xilinx and Altera tools as they will correctly perform STA on the transfers between the domains (just make sure that timing wasn't cut between the clock domains in the timing constraints). As the design was working I'm assuming the design was coded such that there is adequate setup/hold time for the transfers between clock domains (i.e. 4 ns period for transfers to/from the 250 MHz), otherwise you will have to add synchronizing flip-flops to the design.

If the design can't make the synchronous timing arcs between clock domains, then you better check every one of the arcs as the original design was probably not handling the clock domain transfers correctly. You may want to verify that anyway.

Regards